OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [README] - Rev 716

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 5129d 17h /openrisc/trunk/orpsocv2/boards/README
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5133d 07h /openrisc/trunk/orpsocv2/boards/README
71 ORPSoC board builds, adding readmes julius 5387d 23h /openrisc/trunk/orpsocv2/boards/readme.txt

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.