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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [orpsoc_top/] [orpsoc_top.v] - Rev 544

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Rev Log message Author Age Path
544 ORPSoC ordb1a3pe1500 update - adding SD card controller. julius 4933d 12h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5043d 12h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5103d 06h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 5136d 08h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5136d 20h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v

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