URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [Makefile.inc] - Rev 480

Rev	Log message	Author	Age	Path
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	5067d 23h	/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc
468	ORPSoC update: Added USER_ELF and USER_VMEM options to reference design simulation scripts. Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path ML501's board.h bootrom default now boot from SPI	julius	5076d 19h	/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc
425	ORPSoC update: GDB servers in VPI and System C model updated to deal with packets gdb-7.2 sends. Documentation updated. Reference design tests can now be run in or1ksim (added rule to sim/bin/Makefile). or1200-except doesn't appear to work as illegal instruction error isn't causing jump to vector. Updated Or1200 tests to report test success value and then exit with value 0.	julius	5130d 04h	/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	5144d 03h	/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc