URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [syn/] [synplify/] [bin/] [Makefile] - Rev 415

Rev	Log message	Author	Age	Path
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5132d 02h	/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	5136d 04h	/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	5137d 16h	/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile