URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [include/] [ddr2_model_preload.v] - Rev 412

Rev	Log message	Author	Age	Path
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5134d 20h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/ddr2_model_preload.v