URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [include/] [ddr2_model_preload.v] - Rev 439

Rev	Log message	Author	Age	Path
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5120d 06h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/ddr2_model_preload.v
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5123d 20h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/ddr2_model_preload.v