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Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [include/] [eth_phy_defines.v] - Rev 480

Rev	Log message	Author	Age	Path
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	4994d 05h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_phy_defines.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5049d 12h	/eth_phy_defines.v
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5253d 03h	/eth_phy_defines.v
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5412d 10h	/eth_phy_defines.v
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5463d 20h	/eth_phy_defines.v