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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [include/] [synthesis-defines.v] - Rev 439

Rev	Log message	Author	Age	Path
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5123d 20h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/synthesis-defines.v