URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [include/] [or1200_defines.v] - Rev 478

Rev	Log message	Author	Age	Path
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	5046d 19h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	5093d 09h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
426	ORPSoC update Reverted back to previous OR1200 instruction cache. (...which...) Fixed or1200-except test failure on generic model. ML501 build not passing or1200-except test. Tried disabling burst on the bus (memory server doesn't support it yet) to no avail. To be continued...	julius	5106d 08h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5114d 18h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5118d 08h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v