URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [orpsoc_top/] [orpsoc_top.v] - Rev 547

Rev	Log message	Author	Age	Path
530	ORPSoC update Ethernet MAC Wishbone interface fixes Beginnings of software update. ML501 backend script fixes for new ISE	julius	4941d 22h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5082d 16h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5110d 17h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5114d 06h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v