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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_phy_ctl_io.v] - Rev 581

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412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5118d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_ctl_io.v

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