URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sim/] [bin/] [Makefile] - Rev 415

Rev	Log message	Author	Age	Path
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5131d 07h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5134d 21h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
71	ORPSoC board builds, adding readmes	julius	5389d 13h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5393d 18h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5396d 13h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile