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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sw/] [board/] [include/] [board.h] - Rev 485

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Rev Log message Author Age Path
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5041d 11h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5059d 15h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 5067d 12h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5101d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 5120d 20h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5129d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5132d 20h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5391d 17h /board.h
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5394d 12h /board.h

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