| Rev |
Log message |
Author |
Age |
Path |
| 492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
5030d 15h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5047d 17h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
5065d 21h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
5073d 18h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
5100d 08h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5107d 12h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5127d 03h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
5135d 12h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 410 |
ORPSoC: Adding README in root explaining how to build documentation, and
documentation fixup so it builds properly again. |
julius |
5140d 13h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
5140d 14h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
5141d 02h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5144d 13h |
/openrisc/trunk/orpsocv2/doc/orpsoc.texi |
