URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_cpu.v] - Rev 710

Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5168d 20h	/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5170d 11h	/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5413d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5533d 08h	/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v
6	Checking in ORPSoCv2	julius	5647d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v