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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_cpu_registers.v] - Rev 672

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360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5191d 21h /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v
6 Checking in ORPSoCv2 julius 5668d 17h /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu_registers.v

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