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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_wb.v] - Rev 596

Rev	Log message	Author	Age	Path
547	ORPSoC dbg_if fix for slow Wishbone slaves	julius	4912d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5174d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5176d 10h	/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5554d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb.v
6	Checking in ORPSoCv2	julius	5653d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb.v