OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_wb.v] - Rev 415

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.
julius 5189d 22h /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5191d 13h /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5569d 21h /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb.v
6 Checking in ORPSoCv2 julius 5668d 09h /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.