URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_clockgen.v] - Rev 502

Rev	Log message	Author	Age	Path
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5105d 05h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5138d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5140d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_clockgen.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5192d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_clockgen.v
6	Checking in ORPSoCv2	julius	5668d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_clockgen.v