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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_fifo.v] - Rev 497

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Rev	Log message	Author	Age	Path
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	5045d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5105d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5138d 09h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5140d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_fifo.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5192d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_fifo.v
6	Checking in ORPSoCv2	julius	5669d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_fifo.v

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