URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_outputcontrol.v] - Rev 478

Rev	Log message	Author	Age	Path
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5125d 15h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5127d 09h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_outputcontrol.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5179d 10h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_outputcontrol.v
6	Checking in ORPSoCv2	julius	5656d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_outputcontrol.v