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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_shiftreg.v] - Rev 762

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Rev Log message Author Age Path
618 Remove unused parameter Tp olof 4880d 22h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v
570 Fix white space in ethmac headers olof 4895d 17h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5119d 20h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.
julius 5152d 22h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5154d 16h /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_shiftreg.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5206d 18h /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_shiftreg.v
6 Checking in ORPSoCv2 julius 5683d 14h /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_shiftreg.v

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