URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_txstatem.v] - Rev 805

Rev	Log message	Author	Age	Path
618	Remove unused parameter Tp	olof	4897d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v
570	Fix white space in ethmac headers	olof	4912d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5169d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5171d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txstatem.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5223d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txstatem.v
6	Checking in ORPSoCv2	julius	5699d 22h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_txstatem.v