URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [ethmac.v] - Rev 630

Rev	Log message	Author	Age	Path
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5091d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/ethmac.v
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5124d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/ethmac.v
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	5125d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/ethmac.v