URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [xilinx_dist_ram_16x32.v] - Rev 483

Rev	Log message	Author	Age	Path
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5129d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/xilinx_dist_ram_16x32.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5182d 21h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/xilinx_dist_ram_16x32.v
6	Checking in ORPSoCv2	julius	5659d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/xilinx_dist_ram_16x32.v