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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [or1200_defines.v] - Rev 739

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504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4992d 07h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4993d 03h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 4995d 07h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
501 ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default		 julius 4996d 07h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4997d 03h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5030d 16h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 5050d 20h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 5051d 13h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 5058d 19h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 5097d 01h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5125d 06h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5175d 18h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5177d 08h /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5177d 16h /or1200_defines.v
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5178d 02h /or1200_defines.v
348 First stage of ORPSoCv2 update - more to come julius 5180d 12h /or1200_defines.v
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5407d 21h /or1200_defines.v
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5420d 13h /or1200_defines.v
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5462d 09h /or1200_defines.v
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5467d 13h /or1200_defines.v

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