URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Rev 500

Rev	Log message	Author	Age	Path
499	ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup	julius	5003d 09h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	5103d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5131d 12h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5181d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5183d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5186d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_alu.v