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Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Rev 479

Rev	Log message	Author	Age	Path
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	5102d 21h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5131d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5181d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5183d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5186d 08h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_alu.v