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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_cpu.v] - Rev 850

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850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4412d 15h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
814 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4448d 02h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
807 ORPSoC: Commit for bug 85 - add DSX support to OR1200.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85

Also added software tests, and added these tests to default regression test list		 julius 4563d 19h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 5006d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 5007d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 5107d 19h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5135d 23h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5188d 01h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
350 Adding new OR1200 processor to ORPSoCv2 julius 5191d 05h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_cpu.v

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