URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_cpu.v] - Rev 476

Rev	Log message	Author	Age	Path
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	5111d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5139d 21h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5191d 22h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5195d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_cpu.v