URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_cpu.v] - Rev 504

Rev	Log message	Author	Age	Path
502	ORPSoC update - or1200, ethmac Xilinx fifos or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default	julius	4986d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
499	ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup	julius	4988d 10h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	5088d 08h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5116d 12h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5168d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5171d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_cpu.v