OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ctrl.v] - Rev 848

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4412d 16h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
537 ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. julius 4947d 22h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 5007d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5136d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5186d 12h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5188d 02h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5188d 11h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 5190d 04h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v
350 Adding new OR1200 processor to ORPSoCv2 julius 5191d 06h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.