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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_fsm.v] - Rev 803

Rev	Log message	Author	Age	Path
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	5062d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5186d 22h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5188d 12h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5188d 21h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dc_fsm.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5191d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dc_fsm.v