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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_fsm.v] - Rev 862

Rev	Log message	Author	Age	Path
849	or1200: Fix for cache bug related to first_{hit\|miss}_ack Under certain circumstances, when first_hit_ack and first_miss_ack is asserted at the same time, cache data would wrongly be overwritten with bus data. Patch by: Matthew Hicks <firefalcon@gmail.com>	stekern	4446d 22h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	5095d 20h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5220d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5222d 08h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5222d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dc_fsm.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5225d 12h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dc_fsm.v