URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_ram.v] - Rev 476

Rev	Log message	Author	Age	Path
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	5051d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5177d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5180d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dc_ram.v