OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dpram.v] - Rev 853

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4866d 20h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.
julius 4894d 22h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5013d 11h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
350 Adding new OR1200 processor to ORPSoCv2 julius 5016d 15h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dpram.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.