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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_du.v] - Rev 848

Rev	Log message	Author	Age	Path
815	OR1200 debug unit: prevent deadlock when trap instruction stalls As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>, the debug unit could deadlock with the instruction decoder if the trap instruction is held back by a pipeline stall. This change prevents that. The problem can be reproduced by placing a breakpoint at an unfavorable position with instruction cache enabled. In our test, this occurred with or1200-cbasic when placing a breakpoint at test_bss using gdb, but this is dependent on such factors as cache parameters and compilation result.	yannv	4436d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5190d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5191d 15h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5192d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_du.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5194d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_du.v