URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_freeze.v] - Rev 762

Rev	Log message	Author	Age	Path
499	ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup	julius	5026d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5205d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5206d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5207d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_freeze.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5209d 22h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_freeze.v