URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_gmultp2_32x32.v] - Rev 762

Rev	Log message	Author	Age	Path
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	5126d 12h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5204d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5206d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5207d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_gmultp2_32x32.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5209d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_gmultp2_32x32.v