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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_fsm.v] - Rev 762

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477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.
julius 5080d 06h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 5147d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5151d 11h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5206d 18h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.
julius 5207d 03h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ic_fsm.v
350 Adding new OR1200 processor to ORPSoCv2 julius 5209d 22h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ic_fsm.v

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