URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_ram.v] - Rev 486

Rev	Log message	Author	Age	Path
483	ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance testing build.	julius	5054d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
482	ORPSoC updates - adding parity checking RTL, ethernet MAC FIFO buffer updates. Software changes.	julius	5058d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	5063d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	5063d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5189d 12h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5192d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ic_ram.v