URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_immu_top.v] - Rev 702

Rev	Log message	Author	Age	Path
679	Allow setting the boot address as an external parameter. If no parameter is used, the value from OR1200_BOOT_ADR will be used Signed-off-by: Olof Kindgren <olof@opencores.org> Acked-by: Julius Baxter <juliusbaxter@gmail.com>	olof	4645d 09h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5123d 12h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5182d 09h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5182d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_immu_top.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5185d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_immu_top.v