URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_mult_mac.v] - Rev 393

Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5186d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5188d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5188d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v
356	Added new simple MAC test to ORPSoC test suite: * orpsocv2/sw/or1200asm/or1200asm-mac.S: Added Fixed MAC pipeline issue in OR1200 * or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn. * orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: "" * orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version * orpsocv2/sim/bin/Makefile: Added new MAC test to default tests	julius	5189d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5191d 11h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v