OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_mult_mac.v] - Rev 829

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
537 ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. julius 4956d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
505 OR1200 overflow detection fixup

SPIflash program update

or1200 driver library timer improvement		 julius 4995d 04h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 5015d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
501 ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default		 julius 5016d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 5016d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 5116d 19h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5195d 11h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5197d 01h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5197d 10h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5197d 19h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v
350 Adding new OR1200 processor to ORPSoCv2 julius 5200d 05h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.