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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_sprs.v] - Rev 833

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Rev	Log message	Author	Age	Path
807	ORPSoC: Commit for bug 85 - add DSX support to OR1200. http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85 Also added software tests, and added these tests to default regression test list	julius	4553d 05h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v
502	ORPSoC update - or1200, ethmac Xilinx fifos or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default	julius	4995d 10h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v
456	ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default.	julius	5070d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5175d 20h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5177d 11h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5177d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v
353	OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. * or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: "" * or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: "" * or1200/rtl/verilog/or1200_except.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_except.v: "" * orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some Verilator related Lint issues fixed. ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and updated RAM model hooks for new RAM. * orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping * orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: "" * orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping, change include and classes for new RAM model. * orpsocv2/bench/sysc/src/OrpsocAccess.cpp: "" or_debug_proxy - fixing sleep and Windows make issues: * or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly * or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated) ORPmon play around, various changes to low level files.	julius	5179d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5180d 15h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v

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