URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_top.v] - Rev 430

Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5172d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5173d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5176d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_top.v