URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_top.v] - Rev 486

Rev	Log message	Author	Age	Path
483	ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance testing build.	julius	5057d 21h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	5066d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5191d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5193d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5196d 08h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_top.v