URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_tt.v] - Rev 787

Rev	Log message	Author	Age	Path
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	5113d 15h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_tt.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5168d 10h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_tt.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5168d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_tt.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5171d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_tt.v