URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_tt.v] - Rev 483

Rev	Log message	Author	Age	Path
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	5135d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_tt.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5189d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_tt.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5190d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_tt.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5192d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_tt.v