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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_wbmux.v] - Rev 762

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363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.
julius 5205d 04h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5206d 18h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.
julius 5207d 03h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_wbmux.v
350 Adding new OR1200 processor to ORPSoCv2 julius 5209d 22h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_wbmux.v

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